Difference between reg and wire

[ASIC_intl]

difference between reg and wire in verilog

What are the differences betwwen net (e.g. wire) and register in verilog. I know that register can store the value until or unless another value replaces them. But net also has same property.

Is the following syntax acceptable inside a verilog module?

wire a;

initial
begin
a = 1'b0;
end

 

[boardlanguage]

difference between wire and reg in verilog

What are the differences betwwen net (e.g. wire) and register in verilog. I know that register can store the value until or unless another value replaces them. But net also has same property.

Is the following syntax acceptable inside a verilog module?

wire a;

initial
begin
a = 1'b0;
end

In traditional Verilog-2001, no that is illegal. Nets/wires do not allow procedural-assignments.

In Systemverilog, the definition of wire is expanded, so I think procedural-assignments are allowed.

 

[ljxpjpjljx]

verilog wire reg difference

So we'd better to know the basic idea of the reg and wire!

 

[ASIC_intl]

verilog difference between wire and reg

So the difference between reg and wire still has not been answered. The question still remains!

 

[ASIC_intl]

verilog reg wire difference

Hi pini_1

But nets can also store values as reg can.

We can declasre the following statement:

wire a_name = 1'b0.

So wire here is storing the value logic zero.

Again in a code of mux in Verilog in behavioral we declare the output as reg. But in a mux there is no necessity of the output to store the value. The dataflow description of a mux for the same reason do not need to declare the output as reg.

 

[vinun_7]

diff between reg and wire

Reg can be used as a sequential element. But wire cannot be.
Reg can be driven from an intial/always block.

Hi pini_1

But nets can also store values as reg can.

We can declasre the following statement:

wire a_name = 1'b0.

So wire here is storing the value logic zero.

Again in a code of mux in Verilog in behavioral we declare the output as reg. But in a mux there is no necessity of the output to store the value. The dataflow description of a mux for the same reason do not need to declare the output as reg.

 

[tkkg3000]

difference between logic, reg and wire

Hi pini_1

But nets can also store values as reg can.

We can declasre the following statement:

wire a_name = 1'b0.

So wire here is storing the value logic zero.

Again in a code of mux in Verilog in behavioral we declare the output as reg. But in a mux there is no necessity of the output to store the value. The dataflow description of a mux for the same reason do not need to declare the output as reg.

Hi ASIC_intl,

I agree with you that wire can store value as reg can.
However,you must focus on the main different points between reg and wire as follows:
Reg:

- Always reg is used in sequential logic:
Ex:
reg q;
always @(posedge clock or negedge reset)
begin
if(reset)
q<=0;
else
q<=d;
end
-Alaways reg is used in combinational logic that is generated by "always loop":
Ex:
reg a;
always @(c or d or e)
begin
case(....)
...: a=c;
...: a=d;
...: a=e;
endcase
end
Wire:

It can simply understand that wire is the connection in the circuit.Therefore,in RTL,you can generate wire by these code lines:

wire a;
assign a=(...);

You can clearly understand this point when you synthesize an RTL code.
Hope it is an useful answer.

 

[ASIC_intl]

what is the difference between wire and reg

hi tkkg3000

Suppose you wrote a mux inside an always block and used a reg variable as the output since always block will only allow registers for procedural assignment.

Secondly you wrote a mux in dataflow using assign statements in verilog. As a result you need not to declare the output as reg. Your output will be wire then.

Do not u think that the characteristics of the outputs in the two above cases are different because in first case the output is a reg and in the second case the output is a wire.

Again some documents clearly write that wires cannot store value whereas reg can. But we saw here that wires can also store value.

 

[FvM]

diff betweeen wire and register

I you are targetting at RTL, you should analyze the problem as a question of hardware structure rather than a question of Verilog syntax to my opinion. You can store a signal in a clock synchronous flip-flop or in an asynchronous latch (which is actually realized as a combinational logic loop with most PLD). In most designs, flip-flops are the appropriate storage method, assuring defined timing and predictable behaviour. Asynchronous latches are issuing warnings with most synthesis tools, they are suspected as unintentional design artefacts. They are necessary design elements in some cases anyway. E.g. the address latch at a multiplexed AD bus has to be asynchronous for optimal timing margin.

 

[koppolu1981]

wire and reg difference in verilog

Here is one more difference between wire and reg come from the simulation point of view.

The value of wire(0on R.H.S) is evaluated for every simulation delta/ change in simulation time, where as the reg is evaluated only when there is change in any of the signal in the sensitivity list. That is why even though the combo logic implemented using assign/procedural blocks is functionally same but has the above difference. Also, because of the above behavior we say that reg need to store the value it has until there is a any change in the sensitivtiy list.

ASIC_intl,
Hope the above explaination would have answered your query. Let me know for any clarifications.

Regards,
RamaMohan

 

[vipulsinha]

difference between wire and reg

This distinction is a difficult one for beginners to grasp but it is important for distinguishing between computer programs and hardware models. But briefly, a reg is like a programming language value. Once a value is assigned to a reg, which can only occur in procedural Verilog constructs, its value is retained until another procedural assignment is made. A wire corresponds to a circuit wire. It has declarative constructs such as gates and continuous assignments driving it and has loads which are input to other declarative Verilog constructs. If a wire has more than one driver, whenever a driver changes value, all drivers are evaluated to determine the winning value (strongest 0 component and 1 component strengths). When all driving value of a wire are removed (called tristating), the value of a wire reverts to the high impedance (z) value, i.e. the value does not persist. Reg and wire are sometimes lumped together and called nets. Regs can only be assigned to using procedural assignments. A procedural assignment can only occur in initial or always blocks, in tasks, or in functions. Also, wires are scalared (unless declaration prevents scalaring) so that each bit changes and is scheduled separately. Regs are always vectored, so that changing one bit is the same as changing the entire reg and events are always scheduled for an entire reg.

Added after 1 minutes:

This distinction is a difficult one for beginners to grasp but it is important for distinguishing between computer programs and hardware models. But briefly, a reg is like a programming language value. Once a value is assigned to a reg, which can only occur in procedural Verilog constructs, its value is retained until another procedural assignment is made. A wire corresponds to a circuit wire. It has declarative constructs such as gates and continuous assignments driving it and has loads which are input to other declarative Verilog constructs. If a wire has more than one driver, whenever a driver changes value, all drivers are evaluated to determine the winning value (strongest 0 component and 1 component strengths). When all driving value of a wire are removed (called tristating), the value of a wire reverts to the high impedance (z) value, i.e. the value does not persist. Reg and wire are sometimes lumped together and called nets. Regs can only be assigned to using procedural assignments. A procedural assignment can only occur in initial or always blocks, in tasks, or in functions. Also, wires are scalared (unless declaration prevents scalaring) so that each bit changes and is scheduled separately. Regs are always vectored, so that changing one bit is the same as changing the entire reg and events are always scheduled for an entire reg.

 

[ASIC_intl]

difference between reg and wire

Hi vipulsinha

U have written that

"Once a value is assigned to a reg, which can only occur in procedural Verilog constructs, its value is retained until another procedural assignment is made."

But when a value is assigned to a wire its value is retained until another assignment is made. So in this regards the wire does not have any difference with a reg.

Is not it?

 

[no_mad]

difference wire reg verilog

Hi,

In a simple words,

wire => real physical wire connection (CONSISTENTLY UPDATED)

reg => it will be able to hold a value.
(a signal being assigned values during certain circuit condition)

That's it.
Hope it helps.

 

[sareene]

declaring verilog output as reg in behavioral

Nets represent connections between hardware elements. The default value of a net is z .Nets get the output value of their drivers. If a net has no driver, it gets the value z.

Registers represent data storage elements. Registers retain value until another value is placed onto them.

 

[ASIC_intl]

reg wire verilog differ

Hi sareene and no_mad

Please note:

Nets can also store values as reg can.

We can declasre the following statement:

wire a_name = 1'b0.

So wire here is storing the value logic zero. This wire again in similar way can be assigned logic high value to hold.

It is in contradiction with both of your implied comment that net cannot store value.

 

[sob]

Re: reg wire verilog differ

Net types: (wire)Physical connection between structural elements. Value assigned by a continuous assignment or a gate output. Register type: (reg, integer, time, real, real time) represents abstract data storage element. Assigned values only within an always statement or an initial statement. The main difference between wire and reg is wire cannot hold (store) the value when there no connection between a and b like a->b, if there is no connection in a and b, wire loose value. But reg can hold the value even if there in no connection. Default values:wire is Z,reg is x.

 

[dave_59]

See https://go.mentor.com/wire-vs-reg

I'm posting to this old thread because this is still one of the top search hits when people are looking to find out about the differences between reg and wires in Verilog. I've just written an article that I hope makes this clearer. Feedback welcome.