Hi every one
The Xilinx FIFO Generator core supports Native interface FIFOs and AXI4 Interface FIFOs
Can you explain me the difference between these two interfaces
thank you
Hi every one
The Xilinx FIFO Generator core supports Native interface FIFOs and AXI4 Interface FIFOs
Can you explain me the difference between these two interfaces
thank you
yes you have write, i have read before this documentation and i still not knowing when we have to choose to use NATIVE FIFO and AXI4 .
as you said that AXI4 is derived from NATIVE FIFO, can you tell me when i have to choose NATIVE FIFO or AXI4
THANK YOU
yes you have write, i have read before this documentation and i still not knowing when we have to choose to use NATIVE FIFO and AXI4 .
as you said that AXI4 is derived from NATIVE FIFO, can you tell me when i have to choose NATIVE FIFO or AXI4
THANK YOU
thank you very much
for me i need to use it with a ddr controller so i have to choose the AXI4.
can you tell me when we have to use the native fifo?
i really appreciate your help
thank you again
thank you very much
for me i need to use it with a ddr controller so i have to choose the AXI4.
can you tell me when we have to use the native fifo?
i really appreciate your help
thank you again
it is quite obvious that in new designs like in designs using vivado IPI you need to use AXI-4.
in old designs (with older ISE versions) you need to use native fifos.