Look like that ECC is just extra 8 bit for error correction.
Single die package (SDP), is one set of memory
Dual die package (DDP), is two set of memory but their data, address and control lines are in parallel within the chip but they have chip select for each die. In this way only one chip can be selected at a time which is also called a rank. This means that with dual die package, we can implement dual rank configuration. It is also to note that dual rank configuration is slower then two single rank configuration because in single rank there will be two single die per packages (SDP) and memory controller can select both at the same time.
Routing two single rank configuration will be more challenging as their will be two independent set of connections between memory controller and each SDP memory chip. Routing dual rank is bit easier as both ranks have parallel connections within in the DDP.
Is it also possible to chose or to run the memories at lower frequency if zynq soc ultra scale don't support it for example ?