Difference between Logic and Reg in System verilog

[nishanthp68]

Hello ,
Logic and Reg in System verilog are 4 state variables and are of user defined size . What is the difference between them .If none what is the use of having two data types?

 

[dave_59]

Legacy.

Verilog initially used the term "Register" for the reg data type, but the 1364-2001 started using the term "Variable" because these things did not always represent a synthesizable register in RTL.

The SUPERLOG language, which was the predecessor to SystemVerilog, created the logic datatype that was slightly different from reg in that it allowed continuous assignments to logic variables, where as Verilog prohibited continuous assignments to reg variables.

SystemVerilog now makes a distinction between datatypes and variables. You can apply a datatype to a variable or a net (wire). However Verilog and SystemVerilog's excessive use of implicit keywords obscures this distinction.

logic A; //is a shortcut for

var logic A;

And

wire A; // is a shortcut for

wire logic A;

The benefit of all this is that you can use typedefs and apply user defined types to add structures and multidimensional arrays to wires. You are also allowed to make a single continuous assignment to a variable of any datatype, so any distinction between logic and reg is now lost.