[SOLVED] Difference between Dual Port Memory and True Dual Port Memory ?

[imbichie]

Hi all,

Please let me know the difference between Simple Dual Port Memory and True Dual Port Memory.

As far as I know in simple dual port memory, there are separate Write data_in_A/address_A/enable_A channel and separate Read data_out_B/address_B/enable_B channels. We can write and read at the same time. But we cannot write and read the same memory location at the same time.

Then in True dual port memory, there are separate Write data_in_A/data_out_A/address_A/enable_A channel and separate Read data_in_B/data_out_B/address_B/enable_ channels. We can write and read at the same time. But I don't know whether write and read the same memory location at the same time.

Please clarify the same.

 

[TrickyDicky]

Usually true dual port refers to a memory with different clocks on both sides. Simple usually has a single clock for both sides.
The read/write clash also has different modes: read-first, write-first and "dont care". This behaviour is usually an IP block parameter, can be done by inferring the ram using a signal or shared variable, or by using an attribute on the memory signal.

 

[imbichie]

Hi TrickyDicky,

In simple Dual Port Memory also we can see separate clocks for read and write.
Please refer to the below link: page 1: figure 1
https://www.xilinx.com/support/documentation/ip_documentation/dp_block_mem.pdf

also in this link : page 44 : Figure 3-4:Simple Dual-port RAM and in page 45 : Figure 3-5:True Dual-port RAM
https://www.xilinx.com/support/documentation/ip_documentation/blk_mem_gen/v8_0/pg058-blk-mem-gen.pdf

 

[TrickyDicky]

Well there you go - Altera and Xilinx differ on their ideas.

Altera True dual port ram: https://www.altera.com/en_US/pdfs/literature/ug/ug_ram_rom.pdf

You can perform any combination of two port operations:
• two reads, two writes, or,
• one read and one write at two different clock frequencies.

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Heres another key point in the Xilinx literature (page 55). Simple dual port means read-only from one port and write-only to the other

The Simple Dual-port RAM is like a
true dual-port RAM where only the Write interface of the A port and the Read interface of
B port are connected

 

[imbichie]

Hi TrickyDicky,

Thanks for sharing these informations.

So as per the Altera point of view,

one read and one write at two different clock frequencies.

is it possible with the same memory location (read and write at the same time)?

 

[TrickyDicky]

Yes
Like I said, and in common with the Xilinx rams, you have a parameter where you can set the behaviour - read-first, write-first or unknown/dont care

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read-first = read old data
write-first = read new data
unknown = magic

 

[vGoodtimes]

@imbichie:
Altera seems to have a more-clear way to do this for mixed port read during write. With Xilinx, each port has a read-first/write-first setting. However, the writing port must be set to read-first in the mixed-port read-during-write equivalent case.