Hello,
Thanks Mr. Freebird and BigBoss,
@Dick_Freebird
Does this mean EM simulating the passives and interconnect and if the process allows it using process/PDK modeling transmission lines if possible for interconnect in the RF path as opposed to the DC path where you can use metal interconnect and not necessarily transmission lines modeled by the kits.
So, in a multistage amplifier then for an RF/mmWave design, maybe doing layout one stage at a time, EM simulating the necessary interconnect and passives and then moving stage by stage to see whether a portion of interconnect or passives along with the extracted transistor affect performance ? Are these good methodologies ?
@BigBoss,
I realize these are huge topics that cannot be discussed in just one message.
Just wanted to make the comment that for low frequency layouts, the EM, matching and parasitics of the interconnect to substrate matter not as much as in RF or MMwave layouts as much. You can use lower level metals it seems, whereas you might want to use higher level metals in high frequency design for interconnect to reduce frequency degradation caused by capacitive coupling to substrate.
Also isolation seems to play a larger role in higher speed circuits for reducing radiation and also substrate noise issues.
Just my general observations, wanted discuss the issues a bit, not get a full explanation which would be too vast.