difference b/w coding in vera and verilog

[pushpa]

Hi,
I wanted to know what are the advantages of using vera over verilog/vhdl? afterall does using vera not cost you additional finances!!

 

[jayant]

since vera is meant for verification you get more flexibility to verify rtl.

 

[wadaye]

Hi pushpa,

It's sure to spend money if you use vera because you need license fee.

People use VERA because it's have some convient Verifical special feature which not

provided by Verilog|Vhdl. To get more information, you'd better study the VERA

language.

 

[aji_vlsi]

Hi,
I wanted to know what are the advantages of using vera over verilog/vhdl? afterall does using vera not cost you additional finances!!

Pushpa,
I recommend you refer to an excellent presentation by SUnderasan K from Broadcom on this topic, it was presented @ Design Verif. Forum-India, bangalore few days back. Tune to dvforum yahoogroups for more.

HTH
Ajeetha
www.noveldv.com

 

[AlexWan]

Hi aji_vlsi,

May you paste the link or file of your recommended presentation by Sunderasan K from Broadcom.

Thanks

 

[mopansen]

Could anybody paste The art of using VERA?