Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
System verilog has features of verilog besides many useful features of VHDL ,System verilog has many objected oriented based features ,system verilog is currently a leading verification language .Actually it's a HDL and HVL .it has many Advanced features than Verilog and primarily used for verification ,Assertion based ,coverage driven etc .Currently most of the mature synthesis tools support verilog /VHDL only but soon System verilog Synthesis will be implemented .Ideally you should learn Verilog before system verilog ,and VHDL too if possible .If you have good verilog coding skills and have learned at least any one of oops languages like c++/java then system verilog learning will be easier .
Verilog is currently the leading HDL for system Design along with VHDL .
System verilog for Verification -Chris Spear
A practical guide for System verilog for Assertion -srikanth Vijaraghavan ,meyyappan ramanathan
Writing Testbenches Using System verilog -Janick bergeron
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.