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Diff pair with active load

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Newbie level 2
Oct 9, 2007
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I have a small doubt in Diff pair using active loads. As shown in fig. Q3 and Q4 are Active loads for Diff pair
Q1 and Q2, As they are connected in Current mirror pattern both the branches (Q1 and Q2) will have same
current flowing through them even differential input is given. Then how would we get differential Output?
Can some body help me on this.

IAppreciate the help.

Yo just have to follow the currents when the circuit is balanced and unbalanced

If balanced:

Q1 I/2
Q2 I/2
Q3 I/2
Q4 I/2
Iout 0

Positive input:

Q1 I
Q2 0
Q3 I
Q4 I
Iout -I

Negative input:

Q1 0
Q2 I
Q3 0
Q4 0
Iout I

Thank you for the help,
If the common mode level is such that both Q1 and Q2 are in active region, and my ac signal is such a way that it is not driving either transistors into cutt-off or saturation,for eg, CM level is +5v, and ac signal is 2V p-p, then both the bases vary from+4 to +6(opp phase), In this case neither of transistors are going into cutt-on, when Q1 base has +6 volts and Q2 is at +4V, the current tries to increase in Q1, the same current is mirrored to Q2 (because of Current mirror structure Q3-Q4). But the base of Q2 is +4V, Current should reduce in it. If current is same then how would output come?

The circuit you're showing is not a fully differential amplifier, but a differential to single-ended converter; Q3 is not an active load, but a diode. For a fully differential output, you need a diode connected Q5 that sets the base emitter voltages of Q3-Q5. Q5 is driven with some reference current (1/2 I).

Now that you do have two active loads, the output common mode level is not reliably defined, so that's your next problem.


The starting point is the biasing current source I:

1) That current I has to flow either through Q1 or Q2
2) As soon as there is a small unbalance, ALL the current would flow through Q1 and none through Q2
3) The current I that flows through Q1 comes from Q3
4) That current is mirrored in Q4
5) Through Q4 there's I and through Q2 there's 0, so, that current has to go through the output line
6) The output, therefore equals -I

PS. You could also think:

1) equal
2) equal
3) Q3 = I/2
4) Q4 =I/2
5) In the output, in one line there is +I/2 and in the other -I/2
6) The output, therefore equals -I


Hi, pavan002
As your schematic, why this circuit is applied generally? Your doubt is the answer.
As you can see, when input voltage vd is unbalance, the difference of collector current of Q3 and Q1 or Q4 and Q2 is not zero, and if you regard either difference as output current, then output voltage is in proportion to the resistance that output current flowing through. That is to say, a very small variation of input voltage vd can cause a large variation of output voltage, if the resistance is large enough. Furthermore, the difference of collector current of Q3 and Q1 or Q4 and Q2 can be decreased, since the suitable output voltage can be obtained by increase the resistance. If the difference of collector current of Q3 and Q1 or Q4 and Q2 is so small that the difference can be ignore, then DC option point is built steadily and input voltage vd is nearly zero. This condition is desired, when we want to construct an operational amplifier.

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