Check Out,
to eval the core area for a core limited design
a) check out the total # of signal pads required. Either it is obtained from front end or is determined from the knowledge of interfaces to the chip.
b) Total area occupied by the modules in the design is calculated. This area is often with respect to NAND equivalents. This is done as apart of calculation of minimum area of chip required.
c) Next step is to find increase in area due to
1) Scan replacement
2) Clock tree insertion
3) HFN on scan enable
4) HFN on async reset
5) Hold fixes on scan chain
6) Hold fixes in functional paths
and calculate Pad overheads with the diagram shown here
or lese, to calculate pad area for a pad limited design check out the aspect ratio and by simple means, get the # of pads along length and breadth of the chip
Height or Width = ( Pad Width * No of pads + Pad Spacing + 2 * Corner Pad width)
Note: The corner pad width is to be taken only if its value > = to Pad Height + Bond Pad Height
Cheers
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Forgot the image