[DFT] Scan Inertion Issues

[maulin sheth]

[DFT] Scan Inertion Issues in DFT Compiler

Hello All,

1) What is the meaning of this warning which was generated during Preview_dft :
Warning : no compatible segment with clock - CLK exist.

Do we need to use create_clock during scan insertion or we can only use the set_dft_signal -type ScanClock ?

2) Also what is the meaning of following warning?
Warning : a non unate path in clock network for clock CLK from pin ...detected.
Is this warning create any issue during scan insertion?

3) How to control Clock gating cells during Scan Insertion. i want specific command to control the clock gating enable signal during Scan insertion.

Thanks & Regards,
Maulin Sheth

 

[assud]

Re: [DFT] Scan Inertion Issues in DFT Compiler

Hi Maulin Sheth,

Let me try to answer your 3rd question on clock gating.
Clock gating can be done manually by using std libraries or with tools. Tools infer the designs where clock gating can be done.
Commands used in DFT Compiler:
' compile -scan -gate_clock ' //inserts clock gating logic
You can specify clock gating control signal using '-usage clock_gating' option of 'set_dft_signal' command.
eg: set_dft_signal -type ScanEnable | TestMode -view spec -usage clock_gating -port port_list

Hope this helps.

 

[maulin sheth]

Re: [DFT] Scan Inertion Issues in DFT Compiler

I have tried to use like -usage clock_gating...but problem is not solved..so the issue is not solved by this...Already there are clock gating cell so no need to insert it..and also no need to do compile with -scan as it is already compiled netlist..Only I need to do stitching..
any other solution?

 

[assud]

Re: [DFT] Scan Inertion Issues in DFT Compiler

ok. can you please explain the clock-gating cell design. Is the clock gating done by the synthesis tool?
Does it makes the design test controllable? Are you getting any DRC violations?
Normal flow is to 'OR' you clock gating enable signal with the scanenable/testenable signal to make it controllable.
If the netlist is without scan controllable pin for clock gating cells, then I guess you will be getting some violations like 'clock not controllable'

 

[maulin sheth]

Clock gating cell is done by synthesis tool with compile -scan -clock_gating..
I have the netlist which is generated after compile..

It is the latch logic for the clock gating cell..it has a Test pin also....Netlist also contain the scan controllable pin for Clock gating...but it will not work,,even autofix is also not work...

 

[assud]

Not work means? can you please share the exact error or violation obtained?
Please clarify whether pre-drc is clear?

 

[maulin sheth]

Autofix will not work means by using autofix configuration in DFT compiler, the clock issue is not solved...so autofix is also not working...
Exact warning is Clock input CP of DFF ff_0 was not controlled. where ff_0 is the instance name.

 

[assud]

As per my understanding, you have got a structural netlist to start with. Please correct me if my understanding is wrong.

Now, we have to take some points into consideration:
- If we are reading a netlist in '.v' format, tool may not infer the 'clock-gating cells' due to attribute missing. Try to read .ddc file, it has the attributes and most probably will solve the issue.
When you do 'dft_drc' , you can tell which all cells get identified as 'clock-gating' through TEST-130 messages, only these cells will get connected by 'insert_dft' command.

If .ddc is not available, evenif clock gating cells are there, tool may not be able to infer it. Please try the following steps:
a) We can trace the 'CP' of DFF and check whether it is controllable by the primary input.
b) CP may be connected to the clock-gating cell as you said, check whether the tool inferred the cell as a clock gating cell using 'report_clock_gating' command
c) If the cell is not inferred, sometimes you need to make the tool re-identify the functional clock that is connected to the clock gate by using 'create_clock' command
d) If it is difficult to identify some clock gates, we can manually specify the test pin connection to the cell (mainly for user initialized clock gates) by ' set_dft_clock_gating_pin' command.

Please let me know if this helps.

 

[maulin sheth]

report_clock_gating command is worked if we declare it as a clock gating..in preview_dft I got the clock gating cell information but report_clock_gating doesn't show..it reports that there is not any user defined clock gating cell.But if I use report_clock_gating_check thn it report the list of clock gating cell...
See I have to stictch the test enable of clock gating cell to scan enable pin...So this is not working...But If I hook up the pin thn it is solved...

- - - Updated - - -

report_clock_gating command is worked if we declare it as a clock gating..in preview_dft I got the clock gating cell information but report_clock_gating doesn't show..it reports that there is not any user defined clock gating cell.But if I use report_clock_gating_check thn it report the list of clock gating cell...
See I have to stictch the test enable of clock gating cell to scan enable pin...So this is not working...But If I hook up the pin thn it is solved...

 

[assud]

If we don't read a .ddc file, report_clock_gating command shows that the tool didnot inferred any clock gating cells. In that case tool won't stitch TE of clock gating to top level scan enable pin while 'insert_dft'.
You can also make sure by pre- dft_drc check (TEST-130 warning).
As we discussed, reidentify clock-gating cells to the tool.

 

[maulin sheth]

I don't have a .ddc file....so it is mandatory to have ddc file for clock gating cells?
In my log there is not any TEST-130 warning....Can you tell me what happened when we doing the hookup_pin in the set_dft_signal?
It will report in the report_clock_gating_check and also clock gating cell report in the preview_dft log file....

 

[assud]

Only the clock gates with TEST-130 messages will have thier test_enable pins connected during insert_dft. .ddc is not mandatory but it is the best way. Team delivering .v netlist would be able to give this file too. If possible, ask for a .ddc file.
Now we only have .v netilist right? In this case attributes are missing and 'insert_dft' will not make TE-SE connection. You can re-identify the attributes by using the 'identify_clock_gating' command. Then check, report_clock_gating and pre dft_drc for TEST-130 violation.
If you manually connect the test pin to top level, then no violations will be reported. If test pin is not connected then it will give TEST-130 warning (will later get connected at insert_dft provided no other violations to the cell). For manual connection, we can use 'set_dft_clock_gating_pin' command.
I am not able to understand, how you used hookup_pin here. Hookup_pins are defined iff tool can take an internal point for its test connections. Can you please share the exact command line?

 

[maulin sheth]

Thanks for replying.
I am using the command :
set_dft_signal -port $port_name -view spec -type ScanEnable -active_state 1 -usage clock_gating.
using this command it is connecting to the clock gating TE pin. But If I use the command :
set_dft_signal -port $port_name -view spec -type ScanEnable -active_state 1 -usage clock_gating -hookup_pin $internal_pin.
Thn all the clock gating cell te pins are connected to particular dedicated clock gated port.
I am not understanding that..I am not getting any test-130 warning...Can I know whay you are more concentrating on the test-130 warning?

Another thing I want to know is -> What is the meaning of no compatible segment with clock available?

 

[assud]

Since you tell that you are able to connect, I am assuming that now the tool is able to infer the clock gating cells in the design.
1. set_dft_signal -port Scan_en -view spec -type ScanEnable -active_state 1 -usage clock_gating
- 'insert_dft' will connect top level Scan_en pin, to TE ports of all the clock gating cells inferred by the tool
2. set_dft_signal -port $port_name -view spec -type ScanEnable -active_state 1 -usage clock_gating -hookup_pin $internal_pin
- tool will connect the <internal_pin> you specified, to TE ports of all the clock gating cells inferred

What is not clear to me is, have you disabled any warnings?
Have you manually connected the 'TE' pins to desired top-level ports? Please check whether the top level connection is already there in clock gate enable pins.
Let me explain the scenarios that usually comes in clock gating for your understanding:
- we have toplevel TM/SE port already connected to the TE pin of clock gating cells:
Here, we don't need the tool to stich again. Use 'set_dft_signal -view exist' :since the scan enable is already routed to the clock gating cells and we need dft_drc to understand that it will be set to a 1 during shift.
- if the above connection is not there:
a) tool can infer clock gating and can stich the enable connection. TEST-130 warnings comes in this case. we need to describe the port details by 'set_dft_signal -usage clock_gating' command
b)tool cannot infer clock gating: make the tool re-define clock gating as I explained earlier and follow steps in case (a)

 

[maulin sheth]

Since you tell that you are able to connect, I am assuming that now the tool is able to infer the clock gating cells in the design.
1. set_dft_signal -port Scan_en -view spec -type ScanEnable -active_state 1 -usage clock_gating
- 'insert_dft' will connect top level Scan_en pin, to TE ports of all the clock gating cells inferred by the tool

Thaks for replying and helping...
I think you are not getting exactly what I want to clarify you.
I am only able to connect when I am use the -hookup_pin...else..
If I am not using the -hookup_pin thn clock gating cell TE pin is not connected to ScanEnable pin...I hope now its clear to you...means as you told the 1st point...That only is not working...Only working with hookup pin..

As I have already told you before that I am not getting any TEST-130 warning...

 

[assud]

For this we need info about clock gating identification.
How you made the tool identify clock gating cells?

 

[maulin sheth]

ok..I am slo thinking that..We need info about clock gating cells.......
My Compiler is not supported for the identify_clock_gating....It shouts error like :
-> command is not available in this version..pl check with next version..

 

[assud]

which DFT Compiler version are you using maulin?

 

[maulin sheth]

Version is : 2010.03