[DFT] Scan Chains ReOrdering

[ivlsi]

Hi All,

When and how scan-chains re-ordering is done? What inputs to the tool? Should RTL designer consider a number of scan chains? What pins can be used for scan chains?

Thank you!

 

[englishdogg]

Its done during the placement stage of the flow, most commonly now also done during physical synthesis as well. the inputs are same that you pass to the PnR tool or the physical synthesis tool - but your scan chains should have been built / connected by then in the netlist and requires a scandef as well.

All have different flows so diificult to say like it is a must for an RTL designer to consider, but its good to have assumed for those pins and RTL engg can names the pins per block to map at the top level architecture as well especially BIST, compression etc. Normal scan chains is difficult as it would be dependent on ff in the block/ design/ module.

 

[ivlsi]

What does RTL Designer should do in order to prepare his/her design for DFT?

Anyway, is it MUST to add the scan-related ports manually to the design or it might be left for the DFT tool?

What about adding scan MUXes? LockUp Latches? Can RTL Designer leave all these issues to DFT Designer and just focus on the functional implementation of his block? Should RTL Designer prepare anything in order to support mixing of clocks in the scan chains?

How LockUp Latches and Clock Gating Latches should be handled during the scan?

What's the BEST PRACTICE?

Thank you

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Why ATPG patterns should be simulated on Netlist? What purpose? I heard it's required to test scan chain connections, but I don't understand why not to use STA, but Gate-Level simulation instead?

 

[rca]

STA does not check any functionality.
Gate simulation with timing of the scan, will confirm that the model used for analog-pad... are correct, and the timing checked during STA is also align.

 

[maulin sheth]

What does RTL Designer should do in order to prepare his/her design for DFT?

Anyway, is it MUST to add the scan-related ports manually to the design or it might be left for the DFT tool?

What about adding scan MUXes? LockUp Latches? Can RTL Designer leave all these issues to DFT Designer and just focus on the functional implementation of his block? Should RTL Designer prepare anything in order to support mixing of clocks in the scan chains?

How LockUp Latches and Clock Gating Latches should be handled during the scan?

What's the BEST PRACTICE?

Thank you

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For DFT, there are some design rules.
e.g. Flops must have asynchronous reset, or reset, clock must be controlled in test mode.
Yes. Designer can leave all DFT stuff, but best practice is that, it must in RTL, so during synthesis, all optimization techniques (area, power ) covered, So if RTL guy add mux, than its good practice.
Lock up latch is very discussed topic, you can find lots of information in this forum also.
Clock gating cells need some test enable architecture, so those cells can be controlled during scan mode.

Hope it helps.

 

[englishdogg]

The best practice -- i would rather go for the most proven practice until your working on a test chip where you may want to try something new.

This topic can have as much as discussion needed and is most suitable over coffee or beer.
Its nots that RTL engineers dont manage DFT at all - many IP teams over years have identified locations where they add test points to increase coverage and now for legacy they are there. Again addition of ports i would say is a small thing can be managed anywhere - but if your not doing any of it then its good to leave it to the DFT team for them to manage it best as per their need / requirement.

Without DFT inserted you cannot manage LockUp / CG so to make it simple - i believe you should leave it to the DF team and nt care.

 

[maulin sheth]

Yes. That is true.
But it is not like that its work of not designer, its only work of DFT.
But we just need to think at chip level only. So we can make chip DFT friendly at RTL level by inserting mux to control clock and reset etc.
After DFT start, if any changes required, thn we can do it at RTL again by taking help of DFT team.