DFT coverage problem

[u24c02]

Hi.

I have some query.

Why does not the DFT coverage 100%?

 

[artmalik]

theoretically it should be 100%....but there are situations where this will not possible because of the design of the cells.
a) use of latches in the design.
b) in certain cases the design uses non-scannable latches for speed. the scan logic reduces the speed of the design. this is done in critical speed intensive design. so if the flop fails the whole system doesn't work so you really don't need to have a scannable flop.
c) places where you have asynchronous interfaces.
there are other situations but the above gives an idea...

 

[rca]

well, if your pads direction could not be changed during the scan for example, you have some points uncovered.
logic path block when test mode is active....

 

[maulin sheth]

We can achieve 100% coverage, but there are some issues. To achieve 100% coverage, design should be DFT friendly like 100%flops are scan flops and controlled, insert test points in combo logic where our EDA tool are not able to reach etc. But due to limitation of area, power and pins, we are ok with some less coverage.