During first run chip's temperature increased so you can violate setup requirement (T higher -> delays higher).
You can try to decrease ATPG clock frequency or decrease chip temperature and check if I right?
During first run chip's temperature increased so you can violate setup requirement (T higher -> delays higher).
You can try to decrease ATPG clock frequency or decrease chip temperature and check if I right?
thanks for your reply, actually when find the root cause, we founded that it is the IO input voltage level is not setting correctly, which will resulting some odd phenomenon. when we setting correct voltage level. the "failing" chip still can work. currently we cannot explain why this phenomenon happen.