mtwieg said:Here's a simplified circuit approximating the behavior of one half of a diff pair with active load.
mtwieg said:Right, that's certainly not how the real circuit is configured. in reality M1 (and all the other loads on the diff pair) is configured as a MOS diode which drives another current mirror to the next stage.
mtwieg said:Now, what is a convenient way to integrate hysteresis into that topology in a way such that the hysteresis is reasonably constant vs Vcm?
Hello, I'm currently doing my first "real" cmos design for fabrication (0.5um 5V onsemi). .
Yeah, I believe it's an MEP run from my school. For this, I'm using Cadence 5.1.Hello, I am sorry that I have no answer for your post.. but I am interesting on the technology you are working with, Are you getting it from MOSIS by using MEP account ??? and please I also would like to know which kind of EDA you are using ?
Thank you
Yeah, I believe it's an MEP run from my school. For this, I'm using Cadence 5.1.
mtwieg said:So I thought I had a cascoded design working well, but it turned out I wasn't biasing things correctly and some transistors were in triode region...
mtwieg said:Not sure why the difference in simulations was so large, my model parameters should be the same...
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?