deviation from ideality of integrator due to parasitic pole

[mujtabaf]

HI,
actualy, i have been assigned to study op-amp integrator by my teacher..
and, i couldnt yet get helpfull stuff regarding non ideality of integraor on net

also, i couldnt get succeed while circuit simulation to feel the effects of unity-gain frequency on integrator ckt., but in real, this parasitic pole cause the ckt to perform the integration operation twice.

thanks in advance.
quick reply will be appreciated.

 

[LvW]

Re: deviation from ideality of integrator due to parasitic p

HI,
actualy, i have been assigned to study op-amp integrator by my teacher..
and, i couldnt yet get helpfull stuff regarding non ideality of integraor on net

also, i couldnt get succeed while circuit simulation to feel the effects of unity-gain frequency on integrator ckt., but in real, this parasitic pole cause the ckt to perform the integration operation twice.
thanks in advance.
quick reply will be appreciated.

Hi mujtabaf,

my recommendation is to concentrate primarily on the phase of the integrating circuit because this is the best way to observe the difference between ideal and real.
The ideal phase difference between input and output is 90 deg (+ 90 deg for inverting and -90 deg for non-inverting circuits).
In fact, this phase shift will be achieved exactly only at one single frequency.
The reason is as follows:
*for low frequencies the finite gain of the opamp (or a resistor across the integrating capacitor) shifts the phase in direction to zero deg;
* for rising frequencies the phase deviation becomes larger due to the second opamp pole.
Thus, the quality of an integrator is described by the frequency range in which the deviation from this ideal value is acceptable.

Added after 4 minutes:

Here comes another tip: If you compare different integrating circuits with each other you will notice that different circuits react in a different way (more or less sensitive) to parts tolerances. This can be observed also by the phase responses. This could be an interesting quality criterion.

 

[mujtabaf]

Re: deviation from ideality of integrator due to parasitic p

thanks to reply.
i haven't connected Resistance in feedback..
therefore, the phase error is only due to non-zero losses in capacitor.

another one thing, my teacher has advised me to more focused on higher frequencies near or greater than frequency of paracitic pole, i-e unity -gain frequency, to observe 2nd pole effects.

but, how? i couldnt understand yet.
one of the approach is to observe phase error.
any other approach??

Added after 1 minutes:

also, at higher frequencies(above 100 Khz), there is a continous vibration in output of integrator.(output is not a smooth one, like input)
can anybody explain it. plz??