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Re: determining the frequency of nco implemented in fpga
You can try to run signal tap from a generated fast PLL clock, e.g. 200 to 300 MHz. Unfortunately it may upset design timing closure unless you declare the respective domain crossings as false path.
Supplementing to what ads-ee already explained. You're no seeing the real frequency of the 50 MHz clock because it's undersampled, counting edges gives an apparent frequency of about 15 MHz (65 - 50 MHz).
You can try to run signal tap from a generated fast PLL clock, e.g. 200 to 300 MHz. Unfortunately it may upset design timing closure unless you declare the respective domain crossings as false path.