Determining the Frequency of a large design

[tariq786]

I want to determine the max frequency of a large design(coded in verilog). I know that one can do static timing analysis. But how to determine which paths are false paths and which paths are multi cycle paths. My design has no multipliers or any thing like that which could aid me determining multi cycle paths.

Secondly, if i determine the frequency using static timing analysis, i am not able to run post synthesis timing simulation using this frequency as i get timing violations such as setup time and hold time.I have to increase the clk period by a factor of 10 or so to get away these timing violations. The question is how to ensure multicycle constraints are being met during post synthesis simulation.

How important is to do post synthesis gate level simulation?I have found it to be very essential to know that synthesis tool has done its job correctly and that your simulation results match the golden (pre synthesis) functional simulation.

Any tutorials or links to complete design cycle will be highly appreciated.


Thanks a lot.

 

[owen_li]

Hi.
For the identification of the false path and multicycle path, I have some comments:
1. communicate with the logic designers. they have better understanding about the design, and will give you some valuable points
2. sort out the 10-20% worst path, after the STA. analyze if there are some timing exception path.
3. I heared that there are some tools who can identifies the false path/multicycle
path. maybe you can google it.

For the highese frequency, I think you should communicate your customer and
your backend team parallelly. In my opinion, you can determine your higheset clock frequency using the slack margin. You can leave a 15%-20% positive slack comparing to the clock period, when you run the Zero wire load timing analysis.

For the gate level simulation, I don't think it is essential before the completion of placement and wiring. we usuallly give the netlist and SDF file back to logic designers. Then they will anotate this file in the logical simulation tool, to see if there are some hold/setup violation when gate level simulation.

Thanks!

 

[tariq786]

Hi Owen_li,
Thanks for you comment. I am a grad student and i am every thing that is i am the logic designer, i am the customer and i am the back end team.

Now what?

Are n't there any examples or tutorials that explain the whole design flow.

Once again thanks for the contribution.