Hi.
For the identification of the false path and multicycle path, I have some comments:
1. communicate with the logic designers. they have better understanding about the design, and will give you some valuable points
2. sort out the 10-20% worst path, after the STA. analyze if there are some timing exception path.
3. I heared that there are some tools who can identifies the false path/multicycle
path. maybe you can google it.
For the highese frequency, I think you should communicate your customer and
your backend team parallelly. In my opinion, you can determine your higheset clock frequency using the slack margin. You can leave a 15%-20% positive slack comparing to the clock period, when you run the Zero wire load timing analysis.
For the gate level simulation, I don't think it is essential before the completion of placement and wiring. we usuallly give the netlist and SDF file back to logic designers. Then they will anotate this file in the logical simulation tool, to see if there are some hold/setup violation when gate level simulation.
Thanks!