I have opted for Iop = 300nA
I recommend to not ascertain a fix value to Io, but take that one which you obtained for an Id value (for W/L=1), accordingly IC, - similar to that Id you want to operate the transistor with. With that value calculate your W/L ratio(s).
... assumed 1/3 of this value for pMOS-I0, then estimated/calculated the necessary W/L ratios to achieve the required UGB for your C0;Hence, I decided to choose I0 around 900nA
I simply took the I0 value which you decided to choose: ... assumed 1/3 of this value for pMOS-I0, then estimated/calculated the necessary W/L ratios to achieve the required UGB for your C0;
gm & gain values were the results.
gm = 34uA/V2
The unit of gm is [(µ)A/V]. Or did you think of the transconductance factor K'=(µo*Cox/2) ?
Iss = 4uA
Fixed input and output CM level to 900mV
M1,2 vth = 497m
vgs1,2 = 545m
normalized voltage, v = 0.69???IC from formula = 1.19
Design Choices of IC
Amplifying Transistors IC = 0.942.
Tail current source IC = 4.217
current mirror load IC = 25.25
Gain = 45 dB
UGB = 550 kHz
gm = 34uA/V
I need to increase the current in order to get more gm.
Yes, it does. 900mV DC
Amplifying Transistors IC = 0.942 : you chose moderate inversion, ok
Tail current source IC = 4.217 : strong inversion, ok for current source
current mirror load IC =25.25 : absolutely wrong, this ruins all the gain from your Amplifying Transistors !
v = normalised overdrive voltage .
After choosing the IC , calculated the normalized voltage,v using the plot between IC and v .
v = 0.69
Vov = v * 2*n * Vt = 0.69*0.07 =0.0483
Vgs = Vth + Vov = 0.545
v = (overdrive voltage Vov )/(2*n*Vt)
Vt: thermal voltage
n = 1.4
From v => Vgs was determined.
Since input common mode level is fixed, I chose the source potential to ensure required Vgs is obtained.
In this case:
Vg= 900mV
Vth = 497mV
Vgs = 545mV and Vg = 900mV
Vs = 355mV (Vds for tail current source)
The common mode level is 900mV. For current 2uA and I0p = 300nA , I obtained this value of IC.
As told by you earlier, the value of Io can't be fixed.
I don't understand how output resistance of PMOS current source (and hence gain) is controlled by W.
Didn't you study my above example? Your current mirror load pair should operate in a similar inversion mode like your amplifying transistors. Operating in (very) strong inversion mode ruins your gain.
Note the different I0 for PMOSFETs.
I don't think so.
BTW: Does your ac voltage source include a DC voltage source (same as at the other diff. input)?
Not by W (alone). W/L, respectively the inversion mode is the reason.
Remember the gm/Id vs. IC curve?
View attachment 141370
I forgot that you need Vg = Vd = 900mV (common mode output voltage), sorry.
And now it seems you need a PMOS input stage. Try something like this: View attachment 141857
I need to design cascode diff amplifer and folded cascode diff amp
But, there are doubts regarding the setup
In differential amplifier,
Output and Input common mode level was fixed.
so, the set-up was quite simple .
Vd =900mV
Vg = 900mV
I had kept tail current source in strong inversion and used IC = 10
In Cascode diff amp , gate voltage at diff pair is known ( input CM level = 900mV)
But, because of the cascode transistor , I am not sure about drain voltage of input pair.
Design specs,
GBW = 1MHz Cl = 10pF
gm = 62.6uA/V
What set-up should be used to determine gmbyid for M1-M2 pair ?
... how to calculate W?
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