Are you sure that (deriv(i("/M0/D" ?result "dc")) is ID's derivative with respect to VGS ? (gm = ∂ID/∂VGS)2. Plot gmoverid using below methods
a) Add gmoverid from function in Cadence Virtuoso
b) Used derivative function deriv(i("/M0/D" ?result "dc")) / i("/M0/D" ?result "dc"))
They give different results
No: SQL = log10 {(ID/ I0)**-0.5 * MAX(gmoverId)}3) Used the formula to determine SQL
log10(ID/ I0)**-0.5) * MAX(gmoverId)
This is ok, because V0 = VDS > VGS...
ISSUES
a. From the reference paper, I have deduced that the transistor must be kept in saturation.
Please do comment on the circuit diagram used for this.
If you can't do it arithmetically (line with slope -1/2 through measured point), try it graphically....
c. In Cadence Virtuoso Visualization and Analysis XL (graphs), I am unable to add tangent function to the plot obtained in step 4)
You have provided above a very useful paper. Here is another one....
I would appreciate if you could provide some references
Is it possible to estimate the technology current from the foundry?
You should get a Technology Current value of a 180nm process, about 0.6 ... 1µA for NFETs.The technology is SCL 180nm. But, my design requires L_min = 500 nm.
No: -1/2 , s. here: View attachment Determination_and_Study_of_MOSFET_Technology_Current_p2.pdfFrom the plot obtained between g_m/ I_D and I_D/I_0 , I find that strong inversion slope (-1) ...
You should get a Technology Current value of a 180nm process, about 0.6 ... 1µA for NFETs.
No: -1/2 , s. here: View attachment 140448
No results to be found!Please find attached the results obtained for with the updated formula.
???... plotting Y vs Y ...
No results to be found!
???
...
In IC based method, choice of technology current strictly dictates the region of operation.
... Now I have two choices:
a. Keep W/L = 1 to get required gm. This doesn't ensure that transistor is in saturation.
b. (W/L) = 3 and get more current . But this will reduce gm
I am designing a CS amplifier
For GBW=1MHz and Cl = 10pF you'll need a drain current of Id=10µA , so W/L=1 should be fine for the NFET(s).
You didn't yet reveal your circuit design.
... is invalid.
Try something like this:
View attachment 140998
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