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details of wireload models

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pandit_vlsi

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smic18_wl10

hi all.
plz give me the details of wireload models.i.e

1.what are these models?
2.why they are used?
3.when they are used?.
4.give an ex:eek:f wireload model?
plz provide somelinks for these....
pandit....
 

zhustudio

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1. Wireload model is used to model wire delay and capacitance in the synthesis stage.
2. Because in synthesis stage, wire delay is not counted in the path delay. As the technology length shrink, the wire delay gives more important role in path delay, equal or larger than cell delay for 130nm to 90nm.
So we need to estimate wire delay in early design stage (Synthesis).

3. To submicro design, 180nm and below. For larger technology length, you can over-constraint the clock to give some margin to wire delay for backend P&R.

4. You can see the wireload model in the liberty file from any synthesis library. Such as
wire_load("smic18_wl10") {
resistance : 8.5e-8;
capacitance : 1.5e-4;
area : 0.7;
slope : 66.667;
fanout_length (1,66.667);
}
Or you can use report_lib command in dc_shell
 

utmseng

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Just want to add something on the question no 4. In the lib format, besides the fanout length, i think DC will be actually using the fanout_capacitance and fanout_resistance to calculate the net delay. (RC delay).

These data can be generated by estimation from physical compiler
 

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