Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

detail definition of parallel case with examples

Status
Not open for further replies.

sun_ray

Advanced Member level 3
Joined
Oct 3, 2011
Messages
772
Helped
5
Reputation
10
Reaction score
5
Trophy points
1,298
Activity points
6,828
What is a parallel case? Can anyone please define it elaborately. Though I have gone through a paper of Sunburst design titled 'Full and parallel case the evil '. But that paper could not define parallel case very clearly.
 

What is a parallel case? Can anyone please define it elaborately. Though I have gone through a paper of Sunburst design titled 'Full and parallel case the evil '. But that paper could not define parallel case very clearly.
i will help.....the thing is that
eg:
case(1'b1)
begin
a1:
.....
a2:
......
endcase


consider the above code,by looking the above code we can understand that a1 will be executed if a1 is 1 ,else a2 is executed if a2 is 1.
what if both a1 and a2 are 1?
such circuit will get synthesize into priority encoders with a1 having higher priority.......so in order to instruct the tool that we need a mux logic rather than a priority encoder ,we use synopsis parallel case
thats it....
 
Last edited:

I think it should be 1 and not zer in your first sentence. The corrected sentence should look like -----a1 will be executed if a1 is 0 else a2 is executed if a2 is 0. Is not it?


Now suppose it happened a1 is zero and a2 is 1 but both a1 and a2 has similar assignment statements. Is it a parallel case then? Can you please elaborate more?
 

Now i have corrected that mistake....
i will help.....the thing is that
eg:
case(1'b1)
begin
a1:
.....
a2:
......
endcase


consider the above code,by looking the above code we can understand that a1 will be executed if a1 is 1 ,else a2 is executed if a2 is 1.
what if both a1 and a2 are 1?
such circuit will get synthesize into priority encoders with a1 having higher priority.......so in order to instruct the tool that we need a mux logic rather than a priority encoder ,we use synopsis parallel case
thats it....
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top