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DesignVisi​on Synthesis Options

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hrithik

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DesignVisi​on Synthesis Options?

Attached is the original multiplier design alongwith its synthesized version.

The problem is that DesignVision (DV) uses the following mappings in the synthesized design.
1) X_Logic0_port <= '0';
This signal gets mapped to one of the inputs of a Full Adder; I want DV to use a half adder instead.
2) FS_1_n4 <= '0';
This signal gets mapped to one of the inputs of a 2-input OR gate; I want DV to use a direct mapping instead (output <= other_input) .
3) FS_1_n3 <= '0';
This signal gets mapped to one of the inputs of a 2-input OR gate; I want DV to use a direct mapping instead (output <= other_input) .
4) FS_1_n2 <= '1';
This signal gets mapped to one of the inputs of a 2-input AND gate; I want DV to use a direct mapping instead (output <= other_input) .

5) In the component "mult4x4_DW02_mult_0", there is a input defined (TC) which is completely unused in its entity and also it is mapped to '0' in the main design.
I need to avoid these ununsed inputs altogether.

What are the compile options I could use in the DesignVision Synthesis tool to achieve these results?
Thanks!
 

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