designing wide swing cascode current mirror

[sachin431]

What is the procedure for designing a very good wide swing cascode current mirror?
Im trying to design a 5uA wide swing current mirror in as in the figure. can someone please suggest a best practice to choose w/l ratio for a given technology node.
Explanation with example is appretiated. Thanks in advance.

 

[deep_sea]

What is the procedure for designing a very good wide swing cascode current mirror?
Im trying to design a 5uA wide swing current mirror in as in the figure. can someone please suggest a best practice to choose w/l ratio for a given technology node.
Explanation with example is appretiated. Thanks in advance.

Hi. One misleading concept in literature is W/L. Actually L is a design parameter that has a major effect on the design. As a general rule, choose large enough L for CS transistors (M7, M1, M3). You might choose 5 times the minimum length. For the cascode transistors, you might choose a smaller L. If you use gm/ID methodology, choose large gm/ID for cascode transistors and moderate (10 S/A or so) for CS transistors. In square law terms, characterise your device at each length you have chosen. Then choose a small Vov (0.13 V) (large W) for cascode and a moderate Vov (0.2 V) for CS transistors.
Then you have to generate the cascode voltage. This is generated by a diode connected transistor with a relatively large L. You have to check that cascode voltage does not violate the conditions for saturation of all other transistors.

 

[sutapanaki]

You can have a look at this tread

https://www.edaboard.com/threads/biasing-of-wide-swing-current-mirror.382799/