Pavan kumar CR
Newbie level 4
- Joined
- Jan 25, 2013
- Messages
- 5
- Helped
- 0
- Reputation
- 0
- Reaction score
- 0
- Trophy points
- 1,281
- Activity points
- 1,316
Dear All,
Currently I'm Implementing digital upconversion on FPGA . Inorder to implement on FPGA i've developed matlab code to derive filter coefficient.Following are the specification for DUC
1) The sampling rate of the input signal is assumed to be 7.68Msps.
2) This signal has to be up-sampled by a factor of 10 to achieve a sampling rate of 76.8 Msps.
Filter design procedure I have followed is
Filter is realized using a three-stage FIR filter chain consisting of
1)single-rate, sharp-transition FIR filter(121 Taps,direct form fir filter cutoff frequency<fs/2)
2)Interpolation by 2 FIR filter (22 Taps halfband polyphase filter)and
3)An interpolation by 5 FIR filter(22 Taps halfband polyphase filter)
I've attached matlab code also pls find in the attachment.
Kindly suggest have done a proper design or not.If there is a mistake in design kindly suggest what should be done.
Thanks and regards,
Pavan kumar C R
Currently I'm Implementing digital upconversion on FPGA . Inorder to implement on FPGA i've developed matlab code to derive filter coefficient.Following are the specification for DUC
1) The sampling rate of the input signal is assumed to be 7.68Msps.
2) This signal has to be up-sampled by a factor of 10 to achieve a sampling rate of 76.8 Msps.
Filter design procedure I have followed is
Filter is realized using a three-stage FIR filter chain consisting of
1)single-rate, sharp-transition FIR filter(121 Taps,direct form fir filter cutoff frequency<fs/2)
2)Interpolation by 2 FIR filter (22 Taps halfband polyphase filter)and
3)An interpolation by 5 FIR filter(22 Taps halfband polyphase filter)
I've attached matlab code also pls find in the attachment.
Kindly suggest have done a proper design or not.If there is a mistake in design kindly suggest what should be done.
Thanks and regards,
Pavan kumar C R
