mpatel said:Hi
5. fine. You have 256 channels, means 256 carrier frequencies. You need to tune your NCO for each carrier frequency to convert the signal at zero-IF
6. 256 to 64*4 is fine but your design will be increased four times. You will have to place NCO, CIC and FIR four times. The only benefit is that your will get 4 parallel output channels. If you do not have such requirement, go for single DDC, it will save your FPGA area.
DO THESE:
1. Make a table for all 256 channels and their corresponding IF frequencies (carrier frequencies).
2. If you choose ADC undersampling then carrier frequencies of your channels will be changed. In that case repeat first step with new carrier frequencies.
3. These carrier frequencies will determine the necessary phase increment values of your NCO. Make a table for each phase increment values corresponding to its carrier freqencies.
4. Select 3rd order CIC and very narrow band LP FIR. If you are using CIC for downsampling then there will be multi-clock domain between CIC output and FIR input. Take care of that issue very well.
Added after 2 minutes:
If I am correct, with webpack license you can run paid IP cores for only one month after downloading into FPGA.
Added after 1 minutes:
Check www.opencore.org
You will get all your IP free of cost and they are technology independent also.
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