Designing a dual port ram from single port rams

[fragnen]

How to get a dual port ram by using single port rams?

 

[KlausST]

Hi,

the most important: you need the timing diagrams of both partners accesing the RAM.

Klaus

 

[ads-ee]

Time multiplex the RAM access by running the single port RAM at 2x the speed of the logic reading and writing the RAM.

 

[fragnen]

Time multiplex the RAM access by running the single port RAM at 2x the speed of the logic reading and writing the RAM.

This may not work in all scenario.

 

[KlausST]

Hi,

May or may not. The timing diagrams will tell. ;-)

Klaus

 

[fragnen]

We want a better solution.

 

[KlausST]

Hi,

So you don't want time multiplex and you don't want true dual port.

Is there any alternative? I don't see any.

Klaus

 

[FvM]

This may not work in all scenario.

Do you mind to briefly describe your scenario?

 

[fragnen]

Do you mind to briefly describe your scenario?

The dual port memory can face any read or write scenario as usual a dual port memory face.

 

[ThisIsNotSam]

I guess you could put a FIFO in front of the memory and queue operations in time so they never overlap. but this solution comes with a latency. it would work well for all scenarios (I think), but it's a hack, not a good solution.

 

[KlausST]

Hi,

it all depends on the timing requirements.

If you know that any READ comes far after any WRITE then the FIFO will work. .. because the WRITE will be delayd. The READ can not be delayd - I think.
If you don´t know.... even "good luck" won´t help.

Klaus

 

[ads-ee]

This may not work in all scenario.

I've used this technique in FPGA designs where a true dual port couldn't be used due to lack of RAM resources. Large RAM with maximum width where doubling the width would double the amount of RAM blocks used, exceeding the devices block RAM count.
As the RAM is running at 2x the read/write clock frequency of the "dual-port" RAM you can access the RAM twice in one clock period. Both accesses are independent and can be either a read or write access to any address.

A true dual port RAM allows independent accesses to different read or write addresses, so the behavior is the same as the 2x clocked RAM. The main issue is the timing as you now have a half cycle setup/hold in/out of the RAM interface with the 1x read write logic.

So in what specific scenario does this not emulate a true dual port?

 

[fragnen]

I've used this technique in FPGA designs where a true dual port couldn't be used due to lack of RAM resources. Large RAM with maximum width where doubling the width would double the amount of RAM blocks used, exceeding the devices block RAM count.
As the RAM is running at 2x the read/write clock frequency of the "dual-port" RAM you can access the RAM twice in one clock period. Both accesses are independent and can be either a read or write access to any address.

A true dual port RAM allows independent accesses to different read or write addresses, so the behavior is the same as the 2x clocked RAM. The main issue is the timing as you now have a half cycle setup/hold in/out of the RAM interface with the 1x read write logic.

So in what specific scenario does this not emulate a true dual port?

It appears it will work in all scenario. Only there is a latency of getting read data of writing a data of T/4 clock cycle of the original clock compared to no such latency from a dual port RAM.

Is there any timing scenario where this will fail compared to actual dual port ram?

 

[KlausST]

Hi,

now you ask us about a timing (scenario).
But it´s your job to provide this to enable us to give good assitance.

Please don´t blame it on us - if you don´t get the expected answers.

Klaus

 

[ads-ee]

It appears it will work in all scenario. Only there is a latency of getting read data of writing a data of T/4 clock cycle of the original clock compared to no such latency from a dual port RAM.

Is there any timing scenario where this will fail compared to actual dual port ram?

You will only see latency differences if you pipeline the read, otherwise what you will see is a read that occurs on a half cycle as the RAM is running at 2x the rest of the logic. In this case a real transparant latch can be used to capture the read data on the first half cycle. A read in the second half cycle will have limited setup time compared to a first half cycle read. Hence my previous comment about tighter timing.

 

[fragnen]

You will only see latency differences if you pipeline the read, otherwise what you will see is a read that occurs on a half cycle as the RAM is running at 2x the rest of the logic. In this case a real transparant latch can be used to capture the read data on the first half cycle. A read in the second half cycle will have limited setup time compared to a first half cycle read. Hence my previous comment about tighter timing.

How can a real transparant latch can be used to capture the read data on the first half cycle? The latch cannot cause the read data a half cycle to brought back at the beginning of the clock cycle for the same clock cycle.

 

[ads-ee]

How can a real transparant latch can be used to capture the read data on the first half cycle? The latch cannot cause the read data a half cycle to brought back at the beginning of the clock cycle for the same clock cycle.

I don't even have a clue what you meant by the above. The latch is there to hold the data from the first half of a clock cycle to the next rising edge of the clock. You obviously haven't drawn the timing diagram (which I won't do for you). FYI the logic outside the 2x clocked RAM is running on only ONE EDGE OF THE 1X CLOCK.

When I went to school drawing out a timing diagram and analyzing a digital circuit was done in the basic digital logic design class. You need to apply those analysis techniques to determine the timing of the circuit. Based on your numerous posts it appears you need a refresher on the subject.