designing a delay circuit using cmos logic

[bunty_22]

hello
i want to design a simple delay circut using logic gates in cadence virtuso.
i tried many circuts like cascading of inverters ,using xor gates but i dint get the correct output.
help me out.

 

[KlausST]

Hi,

What delay time do you expect?

Do you have a clock source? What frequency?

Cascading inverters.... maybe the compiler optimizes them away...

Klaus

 

[bunty_22]

the time delay is about 50 ps

 

[jdp721]

hello
...i tried many circuts like cascading of inverters

Hi, for simulating your ring oscillator, I think in Cadence ADE, you need to set Simulation-> Convergence Aids-> Initial condition-> click on say the o/p node of the oscillator->apply '0 V' in the dialog.

This will help in adding the initial noise for oscillation build up!

Other members can comment further on this.

 

[bunty_22]

okay thank you.