Sep 13, 2007 #1 J jutek Full Member level 4 Joined Oct 21, 2005 Messages 211 Helped 6 Reputation 12 Reaction score 1 Trophy points 1,298 Activity points 3,140 hello i want to design the comparator with nmos input pair and vdd=5V. I want the output to be 0.1V or 1V when input is lower or higher than reference. How to ensure these levels? regards
hello i want to design the comparator with nmos input pair and vdd=5V. I want the output to be 0.1V or 1V when input is lower or higher than reference. How to ensure these levels? regards
Sep 14, 2007 #2 N naalald Full Member level 4 Joined Dec 2, 2006 Messages 216 Helped 30 Reputation 54 Reaction score 5 Trophy points 1,298 Activity points 2,627 Re: comparator's output (Just an idea, not tested yet!) You may use two inverters at the outputs of the comparator and design the inverters to have Vlow's of 0.1V and 1V repectively (Of course you should use two inverters in series for the 1V output).
Re: comparator's output (Just an idea, not tested yet!) You may use two inverters at the outputs of the comparator and design the inverters to have Vlow's of 0.1V and 1V repectively (Of course you should use two inverters in series for the 1V output).