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Designing a clock in behavioral using Verilog

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supamaka

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Hi everyone,
See if you can make out anything of this problem in Verilog.


Design a clock in behavioral to display 24 hour time. The clock has a six digit display (sec., min., hours). There will be a time_set button, an alarm_set button, an hour_increment button, and a min_increment button. The alarm buzzer is being driven by a one bit output signal when alarm=time. The clock can be driven by a signal with a one second period. The set sequence for either time or alarm is: press set, hour_increment, min_increment, and set again to exit.

Design the clock using at least two modules (such as at least time and alarm).
Design the corresponding stimulus module. You need to generate appropriate vectors to set a time and an alarm of your choice.
 

nand_gates

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Re: Problem in VERILOG

This seems to be ur homework!!
The problem is clear and simple you have to write verilog code for the digital clock!
Start with the counters
hours => 00 to 23 BCD counter we need two such counters one for clock and one
for alarm setting
minutes => 00 to 59 BCD counter we need two such counters one for clock and one
for alarm setting
seconds => 00 to 59 BCD counter

Its very easy code these in behavioral verilog code!

Next we need state machine to control these counters with
inputs set_time, set_alarm, inc_hr, inc_min. Note here that 7 segment display will be
shared for both alarm and time display.

I think these hits are more that sufficient for you to start ur job!
 

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