hello,
my btech project is designing 4 bit general purpose processor supporting instructions mov,add in verilog......i m not getting how to design register file and sram in verilog.
can anyone help me plz..
If you're planning to implement it on FPGA you can use block RAM (BRAM). Register files and SRAM are bunch of flip-flops ganged together. You can define these as 2D array in Verilog. In most cases synthesis tools like Xilinx XST will infer distributed/Block RAM.
hello!!!
I am working on verilog..
i am having problem in instantiating a module from conditional statements.
for eg:
if (ren)
decoder (i0,i1,en,d0,d1,d2,d3)
You are mixing up Structural coding style inside Behavioral. You can't instantiate a module INSIDE conditional statement as far as i know. It has to be done outside the IF statement.
Can you elaborate in more detail.. what functionality do you want to achieve?