Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

designfor testability test point insertion

Status
Not open for further replies.

rajusripathi83

Junior Member level 2
Junior Member level 2
Joined
Nov 26, 2012
Messages
22
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Visit site
Activity points
1,441
hi...



plzzzzzzzzzzzzzzzz..........any one can tell me theflow for inserting the user defined test points using the synopsys tools (dft and tetraMax).

detailed flow...


thank you
 

It is given in the DFT Compiler user guide. Or you can open a case with the Support and they can assist you with it.
 

Is scan is already inserted in your design?
If yes, than just do the ATPF fault analysis, and then find the faults which are untestable or undetected...thn only at those instance you need to insert test point at rtl level or directly at netlist.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top