Design vision error opt-1206

[NIJINE]

HI,
i AM facing an problem in design vision like definition is: " The register GT is constant and will be removed..since i declared a signal and i initialized to some value to make it constant.so in Formality also its creating lot of unmatched ports..please help me..I want these constant values for some comparison purposes ....what to next??

 

[soloktanjung]

Hi,

Please look at this thread: https://www.edaboard.com/threads/166610/

Thanks.