Design the PLL with XOR gate PD in simulink

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Hi,
I would like to know how to design the PLL with XOR gate PD in simulink.
Attached is my simulation block. At high input frequency (ex:30MHz) the system is locked, however at lower frequency (ex:100Hz), the system is not locked. Is there any mistake in my model? can someone give advice on this. Thanks

 

Hi schmitt trigger,
The loop filter is PI (proportional integral) type. The transfer function of the LP is (33.2s^3+266.16s^2+517.88s+742.6)/s^3
 

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