Hello guys,
can anyone please give me the complete list of design rules for tsmc 65nm and 90nm processes.i am using a layout tool in which dr can be edited so i want to make a btech project using these rules.please help me out.
Thanks in advance,
Bye
i am using the cadence generic process design kit, and i think it's adequate for layout and simulations. they have the 90nm PDK as well as the 180nm one.
As for TSMC, i am not too sure how you can request them.