design problems about two-stage opamp

[lhlbluesky]

i have designed a two stage opamp with cascode compensation, the following is the circuit diagram, and the design specs are as follows:

clock rate:12MHz
CL:500fF ~ 4pF
Av>90dB
CMIN:0~2.2V (Vth0 = 0.7V)
output swing:0.1~2.2V
power consumption:as small as possible

in my design, the power supply vdd is 3.3V (+-10%), Ca=Cb=800fF, Iss,M0=800uA, Iss,M9=3mA, GBW = 600MHz

but i have a problem, it is very difficult to mke the phase margin PM larger than 60 degree, and i find that, with the increase of CL, PM increases also. this is very strange, so can anyone help me? or give me some related advice?

besides, i want to know the position of poles and zeros of this opamp, and their relation with PM, and the small signal model of this opamp. besides, i have found the small signal model of fully differential opamp of this structure, but not found the small signal model of single ended structure just as the figure shows.

please help me, thanks all in advance, thanks.

 

[lhlbluesky]

i have another question here, when i connect this opamp as an unit gain buffer, its step transient response is very slow (larger than 200ns to settling), but the bias current Iss is enough for SR requirement, what is the possible reason? pls help me. thanks all for reply, thanks.

 

[lhlbluesky]

any ideas for me?