Design of wb synthesizer (3-7G)

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wb pll

Hi,
i am going to design wb synthesizer (3G~7G). now i am using one loop PLL, but the phase noise is not desired.teh desires phase noise is atleast -126dBc/Hz at offset 100KHz. anohther desired parameter is 1ms locktime. would you please help me with the structurethat i can get the desired parameters?
and another question, in a pll i can not reach the phase noise of the VCO which is mentioned in the datasheet, even at the distance of 100KHz of the desired signal, while the loop filter is less than 10KHz? what could the problem be?
tnx

 

[buckaroo]

I think your spec. is not accurate, -126dBc/Hz@100KHz is too tough in 3G~7G range

 

[mmic1978]

I think your spec. is not accurate, -126dBc/Hz(at)100KHz is too tough in 3G~7G range

I think so, maybe it is -126dBc/Hz@1MHz

Best Regards.