library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity alu is
port (
A : in std_logic_vector(7 downto 0);
B : in std_logic_vector(7 downto 0);
OP : in std_logic_vector(2 downto 0);
C : out std_logic_vector(7 downto 0)
);
end alu;
architecture rtl of alu is
begin
process (A, B, OP)
variable tmp : std_logic_vector(7 downto 0);
begin
case OP is
when "000" => -- ADD
tmp := std_logic_vector(unsigned(A) + unsigned(B));
when "001" => -- SUB
tmp := std_logic_vector(unsigned(A) - unsigned(B));
when "010" => -- AND
tmp := A and B;
when "011" => -- OR
tmp := A or B;
when "100" => -- NOT 'A'
tmp := not A;
when others =>
-- Do stuff for everything else;
end case;
C <= tmp;
end process;
end rtl;