design of arithmetic logic unit 8-bit

[marty1990]

I have to make this in verilog,it`s a project for college. I wasn`t as his classes,because i`m working,and i have no clue how to do it, and no time to do it.
He explained me in the picture what i have to do. I have to make an 8biti ALU ,that has to do + on bit, - on bit, AND, OR, negation a on bit... Sorry for my bad english,i`m from Romania(english is what i picked up from movies). So,please help me

 

[mrflibble]

Unrealistic plan: hope someone does your work for you.

Realistic plan: give up the hope someone does the work for you. Try this particular assignment later when you do have time for it.

 

[marty1990]

honestly?it`s an easy job for someone that knows verilog,about an hour?tops. I have to do it these days?maybe that is the biggest problem. I just asked for help,if someone would like to help me,so i can proceed to the next year of the college,i`d deeply appreciate it.

 

[mrflibble]

In which case I wish you good luck with that scenario. Just realize that for the "done in an hour, tops!" you really need clear specs. Clearer specs than the current scanned piece of paper.

 

[marty1990]

tell me what informations do you need, i`m stupid!(i can`t do it myself),that`s why i`m crying for help. I said one hour,because i tought that the teacher would give me something easier to do,so i could get 5 points out of ten(the minimum points to achieve the exam).

https://www.edaboard.com/threads/145750/ ,i think it should look like this but changed :-??, 8bit ALU (i don t know what gate level means), and i only have to do the operations i posted in the first post

 

[mrflibble]

That link is indeed the basic structure, with case statements handling the opcodes + operands. So you could use that as template.

And as I can predict the future: https://www.asic-world.com/verilog/veritut.html

... and also: https://www.asic-world.com/verilog/art_testbench_writing.html Because if this is your first verilog, then you really should try and testbench it.

 

[marty1990]

short reply: I don`t understand a thing, if you have time,explain in more ample words some paragraphs from that program in the link i gave. At least this way,i`ll understand 20% of the program

 

[mrflibble]

A more meaningful use of time would be:

- go over that bit of code, as it is fairly well documented and readible.
- use the tutorial at asic-world to get an idea of what each part of code does
- try and modify the code to fit the requirements on your piece of paper

Then if you run into specific problems ask about that. Otherwise it just becomes "do my work for me", which won't get you many replies...

 

[permute]

gate level is when the code is described in such a way that you, as a human, could determine what logic gates to use to construct the circuit on a breadboard. eg:

always @ (posedge clk) begin
  x <= x_cmb;
end
assign x_cmb = (en and d_in) or (!en and x);

vs

always @ (posedge clk) begin
  if (en) begin
    x <= d_in;
  end
end

 

[BlackHelicopter]

Something to get you started.

Now I have to ask, don't you have a textbook for the class?

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity alu is
    port (
        A  : in  std_logic_vector(7 downto 0);
        B  : in  std_logic_vector(7 downto 0);
        OP : in  std_logic_vector(2 downto 0);
        C  : out std_logic_vector(7 downto 0)
        );
end alu;

architecture rtl of alu is

begin

    process (A, B, OP)
        variable tmp : std_logic_vector(7 downto 0);
    begin
        case OP is
            when "000" =>               -- ADD
                tmp := std_logic_vector(unsigned(A) + unsigned(B));
            when "001" =>               -- SUB
                tmp := std_logic_vector(unsigned(A) - unsigned(B));
            when "010" =>               -- AND
                tmp := A and B;
            when "011" =>               -- OR
                tmp := A or B;
            when "100" =>               -- NOT 'A'
                tmp := not A;
            when others =>
                                        -- Do stuff for everything else;
        end case;
        C <= tmp;
    end process;

end rtl;

 

[mrflibble]

Pssst, the OP said he had to do it in verilog and is presumably new to hdl. So a VHDL example might be one extra bridge too far. But what the hell, it can always come in handy for random google victims looking for a vhdl ALU. Plus it's a good introduction into reality. The reality where Murphy is on duty 24/7. Which means that when you are searching for some verilog code you can only find the vhdl equivalent. So cultivating some translation $k!llz might come in handy. XD

 

[BlackHelicopter]

Hah I just noticed that, guess I wasn't paying attention! sorry in advance to unsuspecting google victims.:lol: