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design of a opamp (2 stage)

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ehs dav

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hi
can some one help me how to design this project? STEP BY STEP PLEASE
i should use hspice

1. Obtain the features below at lowest power consumption possible at FF and SS corners of 0.35um CMOS.

2. Design bias circuits

3. Design proper switching CMFB for two high impedance nodes of OTA

Target features of design are:
Vdd=1.8 V
DC gain > 80 dB
Settling time(0.01%) < 10 ns
Output swing, Vpp =1.4 v
Slew Rate >500V/us
Phase margin > 75
Cload=5pf

The schematic of the design and library of hspice is shown in file.
 

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