I'm currently doing a project on LNA(low noise amplifier) for my final year. Any help or suggestion on design and its improvement is useful for my project.
Hope this becomes a forum of discussion on design of Low noise Amplifier for C band
Specs:
1. Frequency: 3625 to 4800 MHz
2. Noise Figure: less than 3dB
3. S22 : good output return loss
4. S11: good input return loss
5. Noise temperature: 60 deg. K max. (Including LNA & Switching)
6. Gain: 60 dB min.
7. Gain flatness over the band: ± 1.5 dB
8. Gain stability over Temperature: ± 1.5 dB over the band 0.40 dB p-p over 40 MHz
9. Input VSWR: 1.30 : 1
10. Output VSWR: 1.30 : 1
11. I/P interface: WR 229 CPR (G), (Standard feed interface dimensions)
12. O/P interface: N-type (female) connector
13. Group delay: 0.02 ns / MHz max. Linear
0.003 ns / MHz Sq. Max. Parabolic
0.3 ns peak to peak max. Ripple
14. Max. Input Power without damage: 0 dBm
15. Power Output: (@ 1-dB Gain Compression) +10 dBm Min.
16. Output Third Order Intercept (OIP3): + 20 dBm Min.
17. Temperature Range: 0 to +60 °C
18. Reliability MTBF: 48000 hours or better
19. Power Consumption: optimized power consumption
To meet in the same time the 60dB gain, ripple +/- 1.5dB and VSWR 1.3:1 over the band, is not an easy job.
Generally there are no RF systems to need 60dB gain from the LNA. This high gain LNA always will give troubles. No wonder that the spec is looking for a reliability MTBF time, which is unusual for a solid-state Low Noise Amplifier.
The spec maximum input power is 0dBm, but actually the maximum input power should be -50dBm (P1dB @ Pout10dBm - 60dB Gain = -50dBm)
If you design carefully by paying attention the Stability, it's possible to design such LNA using with CasCode configuration with feedback.
But it's not easy.
Will it be a discrete amplifier or integrated ?? If it will be integrated, which process you intend to use ?
If it will have discrete nature, which type of transistors you're gonna use ?
The gain difference between 25dB and 60dB is huge..
For 25dB gain and desired bandwidth you may use a gain block MMIC type schematic with SiGe transistors which are still available from NXP or Infineon:
The Mini-Circuits family of microwave monolithic integrated circuit (MMIC) Darlington amplifiers offers the RF designer multi-stage performance in packages that look like a discrete transistor. Included in this family are the model prefixes to which the biasing considerations in this article...
Will it be a discrete amplifier or integrated ?? If it will be integrated, which process you intend to use ?
If it will have discrete nature, which type of transistors you're gonna use ?
Its a project for the design of LNA which is to be used in the downlink chain of the Ground stations Antenna systems . I want to do it using CMOS technology. I'm Interested in using SKY130PDK/gpdk90/gpdk45 bcs these are the ones that are available in my Uni. Atleast I should show a proof of concept . But the team at that company are trying to do it using keysight ADS.
The gain difference between 25dB and 60dB is huge..
For 25dB gain and desired bandwidth you may use a gain block MMIC type schematic with SiGe transistors which are still available from NXP or Infineon:
The Mini-Circuits family of microwave monolithic integrated circuit (MMIC) Darlington amplifiers offers the RF designer multi-stage performance in packages that look like a discrete transistor. Included in this family are the model prefixes to which the biasing considerations in this article...
Is this something that you want to manufacture?
GPDK is only a playground for learning and testing, there is no real foundry that will manufacture these designs.
OK, Differential CasCode configuration with Source regeneration might give you a desired or near to wanted results.
Here the problem is the stability. at higher Power Gain.
Why I say differential, because make a differential amplifier stable is easier. Also obtaining Low Noise specification with source regeneration is also a common technique.
But I have serious doubts about the model accuracy of those symbolic/tryout processes because I don't have any info about the measurements on wafer.
At the input of this differential amplifier, you can design a balun that has naturally frequency selective behavior.
30-35 dB Power Gain is possible and NF may be around 2-3dB or maybe less.
Can you share any papers on this , I referred to T. lee paper its confusing and I dont know how to extract many parameters required for the design(also its cascade topology)