Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

design delay cell half period

Status
Not open for further replies.
E

ester01

Newbie level 3
Joined
Dec 16, 2012
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,294
delay.JPGHi all
I want to design a circuit that T(out)=1/2 T(in),IS there any delay cell that T(out)=1/2 T(in)?? delay of output signal is half of input signal.
frequency of input pulse is 10MHZ-200MHz.
 
Last edited:

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top