ucf_knight
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Hi all,
I am able to synthesize a design in Synopsys Design Compiler using some standard cell library. I need a transistor-level netlist for simulation in SPICE. How can I do that starting off from Design Compiler?
Thanks
I am able to synthesize a design in Synopsys Design Compiler using some standard cell library. I need a transistor-level netlist for simulation in SPICE. How can I do that starting off from Design Compiler?
Thanks