Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Design Compiler: Rising in frequency ?

Status
Not open for further replies.
Joined
Sep 3, 2007
Messages
853
Helped
66
Reputation
132
Reaction score
16
Trophy points
1,298
Activity points
0
Hi Everybody,
I need to design a synchronizer operating at least at 20 Ghz. I designed a DFF with Design Compiler and using the newest Standards cell library. For this library the maximum frequency constrain for a simple DFF is around 1.3 Ghz. I understood that I can't go further in frequency and that the synchronizer will operate at inferior rate.
1 / Please can some one tell me how to design Digital High speed (Multi-Ghz) devices in VHDL. Is that possible ?

if no

2/ How may I build my synchronizer ? Should I move to design it at the transistor level with the conventional analog design tools ?

Please dont hesitate to poste replies.
Thanks a lot,

Cheers,
Master_PicEngineer
 

Fahmy

Full Member level 2
Joined
Mar 21, 2007
Messages
132
Helped
28
Reputation
56
Reaction score
12
Trophy points
1,298
Activity points
1,973
I guess you will have to build it yourself (at transistor level ) and characterize it and build the necessary lib file for this flip-flop. But you must make sure that the technology you are using is fast enough for building a flip-flop at such high speed.
 

Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top