Hi AdvaRes,
It would be better if you have only the o/p stage of 4X strength and the nand structure can be of either 1X or 2X depends on the need (like the Rise time and fall time at the input of the 2nd stage), but surely we can drop the sizes in the input part (nand stage).
Advantages:
1> area is reduced
2> since the input size is less, the load on the previous stage is reduced, indirectly reducing the power.
Also, the power consumption depends more on the load and the frequency of operation of the nand, then the device sizes.
Is this nand you are doing is for some PLL? (Sorry, out of context question)
Regards,
RDV