manili
Member level 1
Hello all,
I'm wondering to know if it is possible to design an RTL which is acceptable for different types of FPGAs (excluding the resource volume restrictions)?
For example, What would happen if I do not use any sorts of hard-cores and soft-cores? Now, is it possible to synthesize my RTL for both "Cyclone series" and "Virtex series" without any changes (using Vivado and/or Quartus)?
What would happen if I only use soft-cores? Is the design going to synthesize only on the platform which has the IP core?
Thanks a lot.
I'm wondering to know if it is possible to design an RTL which is acceptable for different types of FPGAs (excluding the resource volume restrictions)?
For example, What would happen if I do not use any sorts of hard-cores and soft-cores? Now, is it possible to synthesize my RTL for both "Cyclone series" and "Virtex series" without any changes (using Vivado and/or Quartus)?
What would happen if I only use soft-cores? Is the design going to synthesize only on the platform which has the IP core?
Thanks a lot.