Now that I realize my design wasn't good, from a learners perspective, I would like to know what are the problems in such a design(briefly)?
In general, a design with internally generated clocks likely would fail if tested while varying the temperature of the device either with a heat gun or cold spray or by building a lot of them (like what happens when you have an actual product, not a lab demo). The reason it would fail is that timing requirements would have been violated. The reason for the timing violation is that when you generate a clock and then use it to clock flip flops, the following occurs:
- The generated clock is offset (skewed) relative to the main clock simply because the main clock is used to generate the generated clock. If the clock is generated with logic, then there will be a propagation delay through the logic; if the clock is generated as the output of a flip flop there will be a clock to output delay.
- Input signals that originate from the main clock will have a similar offset relative to the main clock
Now ask yourself, if you have an input to clocked logic and the clock itself are both offset a bit from the main clock then how do you know which one arrives first at some downstream flip flop? The answer is that you can't guarantee that the data won't beat the clock or at least get there soon enough that either the setup or hold time requirements relative to the generated clock will not be met. If you happen to have a design that might not have any inputs (like the HH:MM:SS clock, which just runs), then you can get lucky and have it all work. But there isn't much call for such designs in the real world, so pretty quickly your luck will run out.
Inside an FPGA, there is little real control over routing and delays so there isn't anything that you can do to guarantee that your design will work when you use generated clocks other than to treat the main clock and the generated clock as you would two asynchronous clock domains and synchronize inputs as they cross between clock domains. So, inside an FPGA, it is far, far better to generate clock enable signals and use those inside a clocked (by the main clock) process. Inside an ASIC, things are different because you do have at least some control over individual net delays.
Kevin Jennings