Design a digital clock using FPGA

[Mumba]

hello
can some one help me with this:
Build a digital clock using FPGA.

Using the DE0 Board you have to program in Verilog a Digital clock that shows:

1- Seconds, Minutes and Hours.

2- Since the board hase only four 7-segment Led displays a solution to display the seconds can be found to show the seconds only when asked. By pushing a button for example.

3- Use the oscillator on the board as the basic clock.

4- Other personnal functionalities are also allowed.

thanx

 

[ads-ee]

So what do you expect us to do? Do you want us to do your homework for you?

You should work on this yourself so you'll learn something. When you get stuck you can post the code and a description of the problem and we can help you find/fix the problem so you can continue working on your project.

 

[dpaul]

Hi thread-starter,

"ads-ee" is correct! This is a very simple project good enough for beginners to learn RTL coding and use basic FPGA functionalities.

I can give you some hints...
You need to use 3 different clocks - seconds, min and hrs. Use the FPGA board clk and feed it to your custom clk-divider module (you need to design it) to obtain a 60Hz (1 second) clk signal. This will be your seconds clock. Using this signal you can generate the minute and hour clock. Using these clocks you can output the sec, min, hrs values to the board display. Start counting from 00:00 when an external button is pressed.
It is just a matter of designing counters and to pass signals from one process() to the other in an RTL code.

 

[K-J]

I can give you some hints...
You need to use 3 different clocks - seconds, min and hrs. Use the FPGA board clk and feed it to your custom clk-divider module (you need to design it) to obtain a 60Hz (1 second) clk signal.

In an FPGA, you do not want to be generating internal clock signals and using them as a clock. Instead what you would do is create clock enable signals (in this case for second, minute and hour) and clock everything with the FPGA board clock. Ignoring this advice is an invitation to having timing problems with your design.

Kevin Jennings

 

[dpaul]

Hello KJ,

Understand my reply was confusing.
I meant only 1 i/p clk to the RTL design which would be the clk from FPGA board - one source clock. The sec, min and hrs are to be generated and used within the design.

 

[ads-ee]

Hello KJ,

Understand my reply was confusing.
I meant only 1 i/p clk to the RTL design which would be the clk from FPGA board - one source clock. The sec, min and hrs are to be generated and used within the design.

I don't think either KJ or I misunderstood you. You are once again saying to generate a sec, min, and hrs clocks from counters using your one input clock source. The fact that you are using a counter to make a NEW clock inside the FPGA fabric is a problem.

KJ is saying you should use a single clock and use enables to only allow updates to registers at the sec, min, and hrs intervals.

clk-divider module (you need to design it) to obtain a 60Hz (1 second) clk signal

If your custom clk-divider module is designed to produce a 60Hz signal it sure won't be 1 second period. A 1 Hz signal has a 1 second period.

 

[dpaul]

Actually I had done such a design during my Uni days and implemented it on an FPGA. Simply my VHDL code on Xilinx FPGA using a DO14 extension kit could display H.H:M.M or M.M:S.S as needed. There was no experienced person to check my design and I got my credit points solely based on the fact that all the project deliverables were met.

The fact that you are using a counter to make a NEW clock inside the FPGA fabric is a problem.

Now that I realize my design wasn't good, from a learners perspective, I would like to know what are the problems in such a design(briefly)?

If your custom clk-divider module is designed to produce a 60Hz signal it sure won't be 1 second period. A 1 Hz signal has a 1 second period.

That was a typo from my side!

 

[TrickyDicky]

Actually I had done such a design during my Uni days and implemented it on an FPGA. Simply my VHDL code on Xilinx FPGA using a DO14 extension kit could display H.H:M.M or M.M:S.S as needed. There was no experienced person to check my design and I got my credit points solely based on the fact that all the project deliverables were met.

This is a problem with "teachers" of VHDL/digital logic design. Their knowledge often comes from work they did many years ago when such designs were the norm, and they've probably been using the same material since then. They normally dont keep up to date with modern practice.

Now that I realize my design wasn't good, from a learners perspective, I would like to know what are the problems in such a design(briefly)?

A clock like this will be affected by PVT (process, voltage, temperature) and routing delays. So the skew will be high because it wont be a on the dedicated clock routing - ie. the clock wont arrive at each register at roughly the same time.
WHen this happens, you start violating setup times from register to register, and the problem can get worse or better as the device heats up. And then because it's affected by routing, the next time you compile it, it will behave differently.

Using a clock enable is better, because the clock is always on a dedicated clock line, and all registers should toggle within a reasonable time of each other, and no setup times are violated.

 

[dpaul]

Thanks TrickyDicky, KJ, ads-ee!

 

[K-J]

Now that I realize my design wasn't good, from a learners perspective, I would like to know what are the problems in such a design(briefly)?

In general, a design with internally generated clocks likely would fail if tested while varying the temperature of the device either with a heat gun or cold spray or by building a lot of them (like what happens when you have an actual product, not a lab demo). The reason it would fail is that timing requirements would have been violated. The reason for the timing violation is that when you generate a clock and then use it to clock flip flops, the following occurs:

- The generated clock is offset (skewed) relative to the main clock simply because the main clock is used to generate the generated clock. If the clock is generated with logic, then there will be a propagation delay through the logic; if the clock is generated as the output of a flip flop there will be a clock to output delay.
- Input signals that originate from the main clock will have a similar offset relative to the main clock

Now ask yourself, if you have an input to clocked logic and the clock itself are both offset a bit from the main clock then how do you know which one arrives first at some downstream flip flop? The answer is that you can't guarantee that the data won't beat the clock or at least get there soon enough that either the setup or hold time requirements relative to the generated clock will not be met. If you happen to have a design that might not have any inputs (like the HH:MM:SS clock, which just runs), then you can get lucky and have it all work. But there isn't much call for such designs in the real world, so pretty quickly your luck will run out.

Inside an FPGA, there is little real control over routing and delays so there isn't anything that you can do to guarantee that your design will work when you use generated clocks other than to treat the main clock and the generated clock as you would two asynchronous clock domains and synchronize inputs as they cross between clock domains. So, inside an FPGA, it is far, far better to generate clock enable signals and use those inside a clocked (by the main clock) process. Inside an ASIC, things are different because you do have at least some control over individual net delays.

Kevin Jennings