Design a common mode (not differential) pipelined ADC?

[jennisjose]

I was trying to design a common mode pipelined ADC?
I am designing for 20MSPS and 10 bit.

I have already designed a folded cascode opamp with a gain of 56dB and Unity Gain Bandwidth 600Mhz. My settling time is 18 ns.

I am using a common mode design(not differential) so Virtual ground plays an important role. I was trying to follow the circuit given in Demystifying switched caopacitor circuits by Mingliang Liu Pg 175 for the 1 bit multiplying DAC. I just have 3 weeks for submitting my project so need help immediately.

I have confusion with the residue part , the virtual ground, the switched capacitor charge charing. Can anyone just tell some documents on the said subject?

As my common mode volatge is 500mV and my Vdd is 1V. My professor said that i should compare at 700mv for positive part and 300mV for negative part. And my Virtual ground is then 500mV.

Thank You

 

[jennisjose]

This is my Amster project report on pipelined ADC design.
I have included as much schematics as possible.

https://jennisjose.webs.com/pipelinedadc.htm